library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity acoplo1 is
Port ( busdatos : inout STD_LOGIC_VECTOR (7 downto 0);
d0 : inout STD_LOGIC;
d1 : inout STD_LOGIC;
d2 : inout STD_LOGIC;
d3 : inout STD_LOGIC;
d4 : inout STD_LOGIC;
d5 : inout STD_LOGIC;
d6 : inout STD_LOGIC;
d7 : inout STD_LOGIC);
end acoplo1;
architecture Behavioral of acoplo1 is
begin
process(busdatos)
begin

	d0 <= busdatos(0);
	d1 <= busdatos(1);
	d2 <= busdatos(2);
	d3 <= busdatos(3);
	d4 <= busdatos(4);
	d5 <= busdatos(5);
	d6 <= busdatos(6);
	d7 <= busdatos(7);
	


end process;
end Behavioral;